1. Field of the Invention
The invention relates to a method for debiting an integrable electronic circuit of a debit card, which contains a nonvolatile, electrically erasable and writable memory that is operated as a multi-stage counter, and which contains a nonvolatile, electrically erasable and writable check memory that has check memory regions associated with the counter stages.
The invention also relates to a circuit configuration for performing the method, having a nonvolatile, electrically erasable and writable memory, which is subdivided into subregions of varying order or significance, and in which control is exerted by circuitry means so that each subregion is erased only whenever a carry bit is written into a previously unwritten memory cell of the subregion of the next-higher order, and having a nonvolatile, electrically erasable and writable check memory, in which one bit is associated with one subregion, and in which control is exerted by circuitry means so that a memory cell of the check memory is written whenever a memory cell of the associated subregion of the memory is written, and is erased whenever the next lesser-order subregion of the memory is erased.
Debit cards are prepaid data carriers which enable payment for goods or charged services, such as telephone calls. These chip cards contain as their essential element a nonvolatile electronic data memory, in which data, such as an amount of money, are stored. The data memory is typically a nonvolatile, electronically writable and erasable memory, of the EEPROM type.
The memory is subdivided into subregions, which are assigned variable order or significance. When the memory is debited, the memory cells are first written in accordance with the units consumed in the lowest-order subregion. Once all the memory cells of one subregion have been written, a carryover to the next-higher subregion takes place, in that an as yet unwritten memory cell is written there, and the lower-order subregion is erased. Once again, then, all the erased memory cells contained in it can be debited or in other words written. In other words, the memory is used as a multistage counter. If the process is interrupted during the course of processing for a carryover, for instance by equipment failure or by violent removal of the chip card from the service-providing equipment, the card can assume a state in which the carryover has already been written into the higher-order subregion of the memory while the lower-order region has not yet been erased.
It is therefore proposed in European published patent application EP 0 519 847 (corresponding to U.S. Pat. No. 5,285,415) that a second, identical counting memory be used, in the counting regions of which the write data of the first counting region are buffer-stored for checking and security purposes. If there is an interruption, it can be ascertained whether the lower-level counter region for a written transfer bit had already been properly erased. The result is better protection to the user against losing money (card debiting) in the case of malfunctions. However, this is attained at a relatively high cost with regard to circuitry for the ghost memory region and the corresponding addressing and control logic. Moreover, variations in terms of production tolerances can cause discrepancies between the two memories, for instance with respect to the magnitude of the programming voltages and the attendant varying programming speeds in the two memories. This can be disadvantageous both to the service provider and to the user. In particular, a card can be intentionally used improperly, by erasing a counter region before a transfer bit has been written.